Course materials
Course materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world and has made them sought after resources in their own right. Course fees include:
Fully indexed course notes creating a complete reference manual
Workbook full of practical examples to help you apply your knowledge
Golden Reference Guide for VHDL language, syntax, semantics and tips
Tool tour guides (to support the tools and technologies of your choice)
Design flow guide for ASIC and the leading FPGA/CPLD technologies

Structure and Content
VHDL for FPGA Design (days 1-3)
The scope and application of VHDL • Design and tool flow • FPGAs • The VHDL world

Getting Started
The basic VHDL language constructs • VHDL source files and libraries • The compilation procedure • Synchronous design and timing constraints

FPGA Design Flow (Practical exercises using a hardware board)
Simulation • Synthesis • Place-and-Route • Device programming

Design Entities
Entities and Architectures • Std_logic • Signals and Ports • Concurrent assignments • Instantiation and Port Maps • The Context Clause

The Process statement • Sensitivity list versus Wait • Signal assignments and delta delays •REGISTER transfers • Default assignment • Simple Testbenches

Synthesising Combinational Logic
If statements • Conditional signal assignments and Equivalent process • Transparent latches • Case statements • Synthesis of combinational logic

VHDL types • Standard packages • Integer subtypes • Std_logic and std_logic_vector • Slices and concatenation • Integer and vector values

Synthesis of Arithmetic
Arithmetic operator overloading • Arithmetic packages • Mixing integers and vectors • Resizing vectors • Resource sharing

Synthesising Sequential Logic
RISING_EDGE • Asynchronous set or reset • Synchronous inputs and clock enables • Synthesisable process templates • Implying REGISTERS

FSM Synthesis
Enumeration types • VHDL coding styles for FSMs • State encoding • Unreachable states and input hazards

Array types • Modelling memories • IP Generators • Instantiating generated components • Implementing ROMs

TEXTIO • READ and WRITE • Using TEXTIO for testbench stimulus and outputs • STD_LOGIC_TEXTIO

Advanced VHDL (days 4-5)
More About Types
Variables • Loops • Std_logic and resolution • Array and integer subtypes • Aggregates

Managing Hierarchical Designs
Hierarchical design flow • Library name mapping • Component declaration • Configuration • Hierarchical configurations • Compilation order

Parameterised Design Entities
Array and type attributes • Port Maps • Generics and Generic Maps • Generate statement • Generics and generate

Procedural Testbenches
Subprograms • Procedures • Functions • Parameters and Parameter Association • Package declarations • Package bodies • Subprograms in packages • Subprogram overloading • Operator overloading • Qualified expressions • RTL Procedures

Text-File-Based Testbenches
Assertions • Opening and closing files • Catching TEXTIO errors • Converting between VHDL types and strings • Checking simulation results • Initialising memories • Foreign bodies

Gate Level Simulation
Rationale for gate level simulation • VITAL tool flow • Reuse of RTL testbench at gate level • Comparison of RTL and gate level results • Behavioural modelling.

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