TOPICS

Course Content

Day 1

The SoC FPGA Altera families with ARM Cortex A9 MP Embedded Processing units
Dichitomy Logic Programmable (User Logic) – HPS (Hard Processor System). Pin-assignment and pin-sharing issues. Rapid introduction to the HPS System blocks (processors, integrated peripherals, Memory Interfaces, Caches and provisions for data integrity and debugging, interconnects and data flow…).

Configuring the HPS
Clocking, Reset, Configuration source, Boot sources, configuring the bridges with the Programmable (User) side.
Practical Exercise: Creating a complete project and Configuring the HPS.

Building the Communication between HPS and Configurable (User) Logic
Reviewing and understanding the different links available, and how/when to use them. Mapping User Peripherals in the HPS memory map. Accessing HPS peripherals from the User Logic side.
Practical Exercise: Golden Hardware Reference Design including a User Peripheral for Digital Signal processing on a stream of data.

Introduction to SystemVerilog BFMs and to the verification environment

Day 2

Hardware to Software Handoff
Principles, tools and files involved. Understanding all the start up phases (from the initial configuration to the working Operating System Linux) with the possible options and boot sources.

SoCAL and HWLIB
Current situation and roadmap. Limitation of bare-metal. AMP vs SMP.

The BSP Editor
Practical Exercise

The ARM Development Environment : DS-5
General functions, code entry, compilation, connection and download to the target. Avoiding pitfalls.

Understanding the Preloader and the tasks it implements
Practical Exercise: generating the preloader, code inspection, inserting user code and bare-metal debug using DS-5.

Combined Hardware-Software debugging
Practical Exercise:Adaptative Debugging and Cross-triggering.

Presenting the available Embedded Operating Systems
The Linux distribution proposed and maintained by Altera.

Using Streamline tools for Real-time Monitoring and Analysis
Practical Exercise.