Course Content – Details
Enquire now to BOOK for the full training course, or please select the module(s) you require from the learning path or links above. Not sure what you need? Use the Quartus II Learning Path above to help you decide or read on to see full details of the content.

Appropriate topics are followed by practical hands-on exercises.
Designing with Quartus II – Foundation (Day 1)
Introduction to Quartus II, the Altera Environment and Altera Devices
Quick Introduction to the Altera offer, the Main Devices families and the Design Environment. Operating Systems supported and Roadmaps. Last version new features.

The Quartus II Design Flow – Part I
User Interface, Environment, Design Entry Methods (HDLs & Text Editors, Megawizard, Schematics and FSM Graphical Entry, Memory Editor, 3rd Party EDA Tools), Project Creation, Device selection, Management basics. Main steps in the Design Flow from entry to compilation.
Practical Exercise

The Quartus II Design Flow – Part II
Constraints and Assignment Editor, Pin assignments, Pin Planner, CSV Import/Export, Place & Route, Fitter control. Download / target programming, JTag chains, dealing with composite chains, using JTag Indirect Programming (JIC), JTag Server and remote use through Ethernet.
Practical Exercise on FPGA board

The Quartus II Design Flow – Part III – Timing Analysis Principles & Introduction to SDC Constraints
Reminders to Timing Analysis Basics, Introduction to the Synopsys Design Constraints format (SDC), SDC Survival Guide, sufficient for Full Synchronous Designs.

The Quartus II Design Flow – Part IV – FPGA Downloading
Download / target programming, JTag chains, dealing with composite chains, using JTag Indirect Programming (JIC), JTag Server and remote use through Ethernet.
Practical Exercise on FPGA board, for SDC and Downloading

Advanced use of Quartus II
Version-compatible databases. Project archival. Creating and comparing Revisions. Using the RTL, Technology & FSM Viewers, Cross-probing. Intelligent Message suppression. Design Rule Checking. Optimization Advisors.
Practical Exercise

Designing with Quartus II – Software Debug and Analysis Tools (Day 2)
Design Flow Automation – Scripting
For improved productivity and quality, design tasks and project management can be automated and secured with command-line scripts and Tcl scripts: Project creation, file management, archival, cleanup, compilation, bitstream creation, result testing, etc…
Practical Exercise on FPGA board

Chip Planner
Concept, applications, use.

Power Estimation and Optimization
Using Powerplay, Early estimation + refined vector-based statistical estimation. Using ModelSim for post-layout timing simulation, using the Msim GUI, and automating with a Tcl Script. Understanding the principles of power reduction at RTL and P&R, using the Power Advisor.
Practical Exercise : using ModelSim and estimating the Power consumption

SSN Analyzer
Concept, applications, use.

In-System Memory Contents Editor + In-System Sources & Probes
Discover these very useful tools, free and easy to use. Concept, Applications, How-To.
Practical Exercise on FPGA board

SignalTap II
Embedded Real Time Logic Analyzers to debug the design in real time. Concepts, creating the STP file, implementation, applications, preparation, compilation, static and dynamic configuration, buffer types, triggering, sampling, data storage & analysis, the PowerUp Trigger, How-Tos. Viewing Real Time captures of State Machines. Scripting.
Practical Exercise on FPGA board

Advanced SignalTap II
Advanced Features of Signal Tap for more complex designs and situations : Storage Qualifier, the PowerUp Trigger, State-Based Trigger flow, Mnemonic Tables, Tapping from Technology Map Viewers. Scripting.

SignalProbe, Logic Analyzer Interface
Take advantage of these (Jtag or not) Instrumentation debugging tools that come with Quartus II at no extra cost to drive an external Logic.

Designing with Quartus II – Timing Analysis (Day 3)
TimeQuest Part I: Introduction, Concepts and User Interface.
Reminders to Timing Analysis Basics. Introduction to the Synopsys Design Constraints format (SDC), STA from the Graphical User Interface and from SDC files. Slack Calculations. Multi-corner Analysis. The TimeQuest STA practical flow. Base Flow with Quartus II.
Practical Exercise.

TimeQuest Part II: Reports and Clock Constraints
Timing Reports, Advanced Reporting, Waveform Analysis, Tcl Scripts, Custom Reports. Cross probing with Quartus tools (Chip Planner, Technology Map Viewer), Synopsys Design Constraints format (SDC): terminology and syntax, Constraining Base, Generated and Virtual Clocks, PLL constraints, Clock Latency, Clock Uncertainty, Metastability & Jitter analysis.
Practical Exercise

TimeQuest Part III: IO Constraints and Synchronous Interfaces
Constraining Combinatorial interfaces, IOs Minimum and Maximum Delays, use of Virtual Clocks, Pin Load and Avanced IO Timing, Reporting IO Timings.
Practical Exercise

TimeQuest Part IV: Asynchronous Paths and Exceptions
Advanced Concepts, Recovery-Removal Analysis, Asynchronous and False Paths, Clock Domains, Crossing management, Clock Multiplexing, Multi-Cycles Paths.
Practical Exercise

Timing Optimization Options
Optimization options, Synthesis Options, Timing Driven Synthesis, WYSIWIG Re-synthesis, Physical synthesis, re-timing, REGISTER duplication. Pros & Cons. Fitter Options.

Design Space Explorer. Concept & use.

Designing with Quartus II – Advanced Timing Analysis (Day 4)
Part I – SDC Reminders and Use of Tcl for TimeQuest
Quick reminders on SDC Basics Timings Constraints. Use of Tcl for advanced and custom Timing Analysis, Command-Line, Custom Reports. Use of Tcl for creation of advanced SDC constraints.

Part II – Timing Exceptions
Advanced concepts on Multicycles Constraints (Setup, Hold). Management of the Timing Exceptions and their Priorities in TimeQuest. Clock Enables analysis, Fanout REGISTESConstraints. Specific custom reports for the Exceptions.
Practical Exercise

Part III – Source-Synchronous Interfaces – SDR
Introduction to Source Synchronous Interfaces. Concepts and use. SDR and DDR schemes, Centeraligned and Edge-aligned. SDC Constraints for SDR Source-Synchronous Input and Output Interfaces. Different case of analysis (FPGA-centric or Board System), Virtual Clocks, PLLs management. Associated Timing Reports.
Practical Exercise

Part IV – Source-Synchronous Interfaces – DDR
SDC Constraints for DDR Source-Synchronous Input and Output Interfaces. Different case of analysis (FPGA-centric or Board System), PLLs/DDIO management. Exceptions. Associated Timing Reports.
Two Practical Exercises (one optional)

Part V – Feedback Design
Concept, analysis and associated constraints. Clock and Data cases. Associated Timing Reports.
Practical Example

Part VI – Timing Analysis for LVDS links
Analysis regarding the hardware used (SERDES, ALT_LVDS, etc …) Transmission and Recption, DPA or not. Constraints, analysis, and Associated Timing Reports.
Optional Practical Exercise

Designing with Quartus II – Timing Closure, Incremental Compilation and Partial Reconfiguration (Day 5)
Optimization Techniques to improve Timing Closure
Advanced Options, Fitter Aggressiveness, Clocks and Global Signals Management (Global / Regional), High Fan-Out Signals, Routing Congestion, Resource Balancing.

Part I – Incremental Flow Introduction
Concepts, Advantages, How-Tos. Techniques to partition a design and achieve better results for complex or challenging designs.

Part II – The Partitions and the Top-Down Flow
Partitions Definition, Recommendations. Critical Paths and Clock Domain Crossing Management, Wrapper Files. Incremental Compilation Advisor. Partition Netlist Types, choice for each compilation. Design Partition Planner. Early or Late Partitioning. Black Boxes Management. SignalTap and the Incremental Compilation. Compilation Time Reduction, Performance Preservation. Top Down Flow.
Practical Exercise

Part III – Floorplanning with LogicLock Regions
Concept and use of LogicLock Regions for Floorplanning. Definition and creation of the different types of regions, use with the Incremental Flow. Early or Late Floorplan. Early Timing Estimate Tool.

Part IV – Team-Based Flows
Implementation of the Team-Based flow, especially for complex projects. Use of Virtual Pins. QXP Netlists. Black Boxes Management. Use of scripts. Recommendations and Restrictions
Practical Exercise

Part V – Partial Reconfiguration
Principles and How-Tos. For Which Projects/Devices. Impact on the Conception Flow.

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