Training materials
This class uses training materials developed by ARM®

Day 1

Cortex-A53 Processor Overview
Cortex-A53 introduction • New features in Cortex-A53
Introduction to ARMv8-A
Architecture versions • Privilege levels • AArch64 registers • A64 Instruction set • AArch64 Exception model • AArch64 memory model
AArch64 A64 ISA Overview
Register set • Load/store instructions • Data processing instructions • Program flow instructions • System control • Advanced SIMD • Cryptographic extensions
AArch64 Exception Model
The AArch64 exception model • Interrupts • Synchronous exceptions • SError exceptions • Exceptions in EL2 and EL3
ARMv8-A Memory Management
Memory management theory • Stage 1 translations at EL 1/0 • Kernel/application space translation tables • Translations at EL2/EL3 • Stage1 tables for hypervisor/secure exception levels • Stage2 tables for virtualized systems • TLB maintenance

Day 2

ARMv8-A Memory Model
Memory types • Memory attributes • Memory alignment and endianess
Caches and Branch Prediction
General cache information • Cache attributes • Cache maintenance operations • Cache discovery
Data barriers • Instruction barriers
Synchronization implementation • Local exclusive monitors • Global exclusive monitors
Cache Coherency
Introduction to coherency • Coherency details for multi core processors • Coherency details for multi processor systems
OS Support
Context switching • Modifying translation tables • Privilege escalation protections • Timers

Day 3

Software Engineer’s Guide to the Cortex-A53
Core overview • Configuration options • Pipeline • Cache logic and branch prediction • Memory management • Interrupts and bus interfaces • Debug features • Power management
Booting a cortex-A53/57 processor in AArch64 • Processor setup
Power management for Cortex-A
Power Overview • Processor Power Modes • Multiprocessor and System Power Modes • Cortex-A Power Modes •
What is virtualization • ARM virtualization support • Memory Management • Exception Handling • Introduction to SMMU
Software stack • Memory system • Debug • TBSA
GIC Programming
Distributor and CPU Interfaces • How to enable and configure interrupts • How to handle interrupts • How to send software interrupts • Security Extensions
Debug infrastructure • Invasive debug • Non invasive debug


A64 ISA workbook
ARMv8 Exception model workbook
MMU and cache initialization workbook.

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