Training materials
The source training materials are provided under license form ARM. This material has been purposely crafted to accomodate the online delivery format.
Session 1
Introduction to ARMv8-A
Architecture versions • Privilege levels • AArch64 registers • A64 Instruction set • AArch64 Exception model • AArch64 memory model
AArch64 A64 ISA Overview
Register set • Load/store instructions • Data processing instructions • Program flow instructions • System control • Advanced SIMD • Cryptographic extensions

Session 2
AArch64 Exception Model
The AArch64 exception model • Interrupts • Synchronous exceptions • SError exceptions • Exceptions in EL2 and EL3
ARMv8-A Memory Management
Memory management theory • Stage 1 translations at EL 1/0 • Kernel/application space translation tables • Translations at EL2/EL3 • Stage1 tables for hypervisor/secure exception levels • Stage2 tables for virtualized systems • TLB maintenance
ARMv8-A Memory Model
Memory types • Memory attributes • Memory alignment and endianess

Session 3
Caches and Branch Prediction
General cache information • Cache attributes • Cache maintenance operations • Cache discovery
Data barriers • Instruction barriers
Synchronization implementation • Local exclusive monitors • Global exclusive monitors
Software Engineer’s Guide to the Cortex-A57/A53
Core overview • Configuration options • Pipeline • Cache logic and branch prediction • Memory management • Interrupts and bus interfaces • Debug features • Power management

Session 4
Booting a cortex-A53/57 processor in AArch64 • Processor setup
Power management for Cortex-A
Power Overview • Processor Power Modes • Multiprocessor and System Power Modes • Cortex-A Power Modes •
What is virtualization • ARM virtualization support • Memory Management • Exception Handling • Introduction to SMMU

Session 5
Software stack • Memory system • Debug • TBSA
GIC Programming
Distributor and CPU Interfaces • How to enable and configure interrupts • How to handle interrupts • How to send software interrupts • Security Extensions
Debug infrastructure • Invasive debug • Non invasive debug

Lab Exercises:
The learning is reinforced with unique Lab Exercises using ARM DS-5 instruction set simulators and covering assembly programming, exception handling and setting up the caches and MMU.

Lab exercises for assembly programming cover the concepts of data processing, flow control, and rely on the development tool-set offered by ARM DS-5.

Exception handling lab exercises look at setting up various execption levels vector table and execution modes as well as executing hypervisor and secure calls.

The Memory management lab takes you though the steps involved in implementing a typical system memory configuration using the MMU.

  • 10 Days
  • 0 Units
  • 0 Hrs

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