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Structure & Content
Definitions, terminology • Functional verification flow and methods • Linting • Simulation • Debugging • Modelling • Coverage • Assertion-based verification • Formal methods

Verification Process
Verification Plan: creation and maintenance • Verification strategy • Test definition, generation and execution • Re-usable verification IP • Milestones and code reviews • Regression and stress testing • Verification metrics and bug-tracking

HDL testbenches • Testbench architecture • Bus Functional Models and data modelling • Testbench automation • Hardware Verification Languages (HVLs) • Object-oriented and aspect-oriented programming • Stimulus generation, directed, random and constrained-random • Response checking and self-checking testbenches • Variable latency, FIFOs and scoreboarding • Coverage-driven methodology and types of coverage

Properties and Assertions
Properties, their definition and use • Temporal properties • Assertions • Authoring of properties and assertions • Observability and functional coverage • Re-using properties

Formal Verification
Definitions, motivation and terminology • Equivalence checking • Property checking • Coverage • Safety, liveness, invariant • Assumptions • Dynamic formal verification

Hardware Prototyping
Hardware acceleration • Emulation and In-Circuit-Emulation (ICE) • FPGA Prototyping • Observability of internal design nodes • Synthesizable assertions

Appendix – Temporal Logic
Boolean algebra • Temporal logic: CTL and LTL • Fairness

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