TOPICS

Course materials
Course materials are renowned as the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world and has made them sought after resources in their own right. Course fees include:
Fully indexed course notes providing a concise Verilog reference
Workbook full of practical examples to help delegates apply their knowledge
Verilog Golden Reference Guide, a quick and complete reference for language, syntax, semantics and tips
Tool tour guides (to support the tools and technologies of your choice).

Structure and Content
Introduction
What is Verilog? • Brief history and current status • The PLI • Scope of Verilog • Design flow • Verilog-2001 • SystemVerilog • Verilog books and Internet resources

Differences between VHDL and Verilog
“Philosophy” • Red Tape • Strong typing • Determinisim • Data abstraction • Structure vs behaviour – Nets vs registers • Language structure – architecture, packages, configurations, files • Identifiers • Output ports • Implicit wires • Arrays • Aggregates • Signedness • Operators • Signal vs variables/nets • Process vs initial/always • if, case, loop differences • File i/o • Hierarchical names

Verilog Basics
Modules & ports • Continuous assignments • Comments • Names • Nets and strengths • Design hierarchy • Module instances • Primitive instances • Text fixtures • $monitor • Initial blocks • Logic values • Vectors • Registers • Numbers • Output formatting • Timescales • Always blocks • $stop and $finish • Using nets and variables correctly

Combinational Logic
Event control • If statements • Begin-endw Incomplete assignment and latches • Unknown and don’t care • Conditional operator • Tristates • Case, casez and casex statements • full_case and parellel_case directives • For, repeat, while and forever loops • integers • Self-disabling blocks • Combinational logic synthesis

Sequential Logic
Synthesising flip-flops & latches • Avoiding simulation race hazards • Nonblocking assignments • Asynchronous & synchronous resets • Clock enables • Synthesizable always templates • Designing state machines • State machine architectures • Verilog code-based FSM strategy • State encoding • Unreachable states & safe design practices • One-hot machines

Other features of Verilog
Verilog operators • Part selects • Concatenation & replication • Shift registers • Conditional compilation • Parameterisation and generate • Hierarchical names • Arithmetic operators and their synthesis • Signed and unsigned values • Memory arrays • RAM modelling and synthesis • $readmemb and $readmemh

Tasks and Functions
Understanding tasks • Task arguments • Task synchronization • Tasks and synthesis • Functions

Test Fixtures
File I/O – Writing to files; File access using MCDs; Reading from files • Automated design verification using Verilog • Force and release • Gate-level simulation • Back annotation using SDF • “Traditional” Verilog libraries • Configuration and libraries • Command-line options • Behavioural modelling

Supplementary Subjects
Behavioural Verilog
Algorithmic coding • Synchronization using waits & event control • Concurrent-disabling of always blocks • Named events • Fork & join • High-level modelling using tasks, Implicit FSMs and concurrent-disabling • Understanding intra-assignment controls • Overcoming clock skew • Blocking and nonblocking assignments • Continuous procedural assignment

Gate Level Verilog
Structural Verilog • Using built-in primitives • Net types & drive strengths • UDPs Gate, net & path delays • Specify blocks • Smart paths • Pulse rejection • Cell library modelling

SystemVerilog
Background • Who is SystemVerilog for? • Current status of SystemVerilog • RTL enhancements • Interfaces • Assertions • Testbenches • C interface.