Training materials
Training materials are renowned as the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world, and has made them sought after resources in their own right. Class fees include:
Fully indexed class notes creating a complete reference manual
Workbook full of practical examples to help you apply your knowledge This includes a tool tour guide (to support the VHDL-AMS simulation tool used in the practical sessions).
VHDL Golden Reference Guide; pocket companion full of syntax, hints, tips and ‘gotchas’ (4-day class attendees only)

Structure and Content
Introduction to VHDL (days 1-2)
The scope and application of VHDL • Design flow • Benefits • Tool and Technology independence • The VHDL world

Design Entities
The basic VHDL language constructs

Files and Libraries
The proper organisation and use of VHDL source files and libraries • The compilation procedure

The process statement and its consequences for simulation and modeling

Sequential Statements
If, case and loop statements w combinational logic and transparent latches • generating test vectors

Defining new data types • modeling tri-state busses w manipulating vectors, using operators • conversion functions • standard packages

More on Types
Making best use of integers and arrays • modelling memories

More on Design Entities
Parameterising designs for re-use • concurrent coding styles • using assertions to report errors

Procedures and functions in test benches and RTL code • understanding packages • operator overloading

VHDL-AMS Workshop (days 3-4)
Review of VHDL 1076-1999 • Maths package 1076.2 • Signal flow modelling in VHDL • 1076.1 (VHDL-AMS) Background

Nature, Terminal, Quantity
Definition of a nature • Terminal nodes • Free quantities • across and through quantities • Electrical package

Simultaneous statements
Simultaneous statements • Implicit quantities • Solvability • Simultaneous if and case statements • Examples: resistor, capacitor, diode

Terminal and quantity ports • Component instantiation • Signal flow modelling

Procedural statements
Sequential programming constructs • Equivalent simultaneous statements • Equivalent functions • Examples: MOSFET, Opamp

Mixed-Signal simulation cycle
Simulation cycle • Initialisation • Break statements • Time step control • Frequency and Noise domain modelling

Mixed-Signal modelling
Mixing concurrent and simultaneous constructs • Events • Examples: ADC, DAC

Pros and Cons of VHDL-AMS
Limitations • Future of VHDL • Object-oriented VHDL • Future of VHDL-AMS.

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