TOPICS

Structure and Content
Day 1
Designing a System on a Programmable Chip (SoPC) using Qsys
Why and when to use SoPC • Introduction to the Nios II processors family and options • Selecting and configuring the Processor, the IPs, the available standard and specific peripherals • The DE0 development Kit • Introduction to the complete Hardware design flow using Qsys and Quartus II.

Practical Exercise: Creating a complete SoPC from scratch, tested on the FPGA Kit.

Introducing the new SoC FPGAs with HPS embedded ARM A9 MP processors
The new device families • General architecture • Hardcore and Fabric dichotomy • Rapid presentation of the ARM Cortex-A9 MP dual core • The SoC FPGA Development Environment.

Introduction to Qsys and Network On Chip concepts
Concepts • Advantages • Drawbacks • Differences with legacy fabric Builder • How to migrate to Qsys.

Validating the Hardware Platform by HDL (co)simulation
Creating the simulation environment • Modeling the Peripherals and the UART • Using ModelSim to simulate the complete SoPC system.

Practical Exercise: RTL Simulation with ModelSim of the SoPC system created previously.

The Qsys Interconnect Fabric
The Fabric • NOC architecture & benefits • The Avalon Interfaces • Miscellaneous kinds of peripheral ports • Transfer and Addressing modes • Generating the Switch Fabric • Adding custom peripherals.

Day 2
Introduction to Custom Peripherals
On-chip or Off-chip peripherals • Creating custom peripherals step-by-step • The Component Editor • Using Tcl scripting • _hw.tcl.

Practical Exercise: Design & use of a simple Custom Peripheral (PWM in VHDL).

System-Level Hardware Optimization
Motivation and concept of Hardware Acceleration • Limitation of traditional architectures • Using Avalon simultaneous multi-master capabilities and the NOC to optimize the performance • Custom Masters, the DMA engines, building hardware accelerators • Custom Instructions : principles, advantages, how to design and use them • CRC calculation example • Custom Peripherals for hardware acceleration • C2H : C code To Hardware compiler (Legacy tool).

Practical Exercise: Accelerating CRC calculation using three different methods and comparing the respective results.

A preview of OpenCL
Principles • The Altera solution roadmap.

The Nios II processor – The Software Development Environment
Main concepts • Software aspects • Introduction to Nios II EDS / Eclipse SBT • Creating a software project • Tools for Compilation and Debugging • Project management • Creating a C/C++ application and associated Board Support Package.

Practical Exercise: Creating a Software Project from scratch, testing it on the Hardware.

Day 3
Software Development using the Command Line flow
Motivation • Compatibility with the GUI • Utilities available to automate the creation of proper scripts • Command line configuration & software download.

Practical Exercise: Using the command line flow and scripts.

Developing Programs for Nios II: the HAL.
Introduction to the Hardware Abstraction Layer (HAL) and programming model for standard basic peripherals: system clock, alarm, time-stamp and high-resolution timers • Programming the peripherals • The role of the data cache • Handling custom peripherals.

Practical Exercise: Using the HAL API to exercise PIOs and Timers.

Introduction to Embedded Software Architectures
System.h • Updating the hardware configuration • Memory mapping • Stack • Heap • The linker • Mastering the boot sequence (alt_sys_init and alt_main) • Hosted vs Free-Standing, optimizing the code size • HAL and file system • Unix-style functions • The Linker script • Stack & Heap • The Boot sequence • The Boot copier • Hosted vs Free-Standing.

Nios II Interrupts & Exceptions
Caveats about legacy interrupts • Presenting the two Interrupts modes and hardware • Pros and Cons of the Cascadable Vectored Interrupt Controller • Using and programming the standard interrupt controller.

Practical Exercise: Enhance the PWM lab to use Interrupts generated by the edge-triggered PIO.

Software aspects of Custom Instructions and Hardware Acceleration
The Optimization flow: Profiling, identifying performance bottlenecks and candidates for hardware acceleration • Using custom instructions • Hardware acceleration through dedicated custom hardware peripherals • Programming API for DMAs, alternative to Altera’s API, issues with Data cache • C2H software perspective (Legacy tool)

Practical Exercise: Simple algorithm • Optimized software implementation • Accelerating with a custom instruction • Hardware acceleration with dedicated hardware block and DMA transfers • Accelerating with C2H • Measuring and comparing performance.