TOPICS

Training materials
This class uses training materials developed by ARM®
Content
Day 1:
ARM Architecture
Architecture version • Registers and instruction sets • Exception model • Memory model • Coprocessors • Architecture extensions • The Future
Cortex-A7/A15/A17 MPCore Overview
New features in Cortex-A7/A15/A17 • big.LITTLE processing
Configuring Caches and Branch Prediction
Cache basics • Caches on ARM processors • L2 and L1 Cache interactions • Cache policies • Prefetching and preloading • Optimization consideration
Using the MMU
MMU Basics • Large Physical Address Extensions (LPAE) • Short-descriptor format • Memory types and attributes • Using the MMU
Introduction to TrustZone
Exception Handling • Memory System • Debug • Software
Day 2:
Multi-Processors/Threads Synchronization
Atomicity • LDREX/STREX Uses • Mutex Implementation
Programming the Interrupt Controller (GIC)
Distributor and CPU Interfaces • How to enable and configure interrupts • How to handle interrupts • How to send software interrupts • Security Extensions
Cortex-A Power Management
Power Overview • Processor Power Modes • Multiprocessor and System Power Modes • Cortex-A Power Modes
Maintaining Cache Coherency
L1 & L2 cache coherency and maintenance • MPCore coherency
OS Support
Multi-Processing • Translation tables • Context switching • Timers
Barriers
Data barriers • Instruction barriers
Day 3:
Multi-Cluster Programming
Introduction • Multi-Cluster Configurations • Miscellaneous Considerations
Booting a Cortex-A7/A15/A17 MPCore
Overview • Booting a single CPU • Booting a cluster
Writing C for ARM
Parameter passing • Floating point linkage • Alignment • Coding considerations
NEON Co-Processor Overview
NEON Instruction Set Overview • NEON Software Support
Virtualization in Cortex A-15
Overview of Virtualization Extensions • Memory Management • Exception Handling
Optional sections:
Performance Monitoring Unit and Trace Functionalities
Invasive Debug • Non-Invasive Debug • MMU • Trace

The Cortex-A7/A15/A17 MPCore are architecturally (ISA) identical and have been purposely designed to work in tandem in a big.LITTLE configuration whilst relying on automated data cache coherency management. This aspect allows us to provide a consolidated training class covering these processors with minimal redundancy.