Training materials
The source training materials include novel content (presentation and labs) developed by supplementing approved training materials provided under license from ARM for ARM Cortex-A9 MPCore software design.
Session 1
Introduction to Zynq
Architecture details with Cortex-A9 MPCore implementation choices
Core and FPGA interfaces
Processing System Built-in Peripherals
Memories and Memory Controllers
FPGA logic and rooting details
I/O Peripherals
Processor System Boot Options
Cortex-A9 core building blocks
Private peripherals
Snoop control unit
Accelerator coherency Port (ACP)
Generic interrupt controller
Core system interfaces

Introduction to the ARM v7 instruction set architecture
ARM v7 Unified Assembly Language

Hands-on Lab session
Assembly Language Basics
Assembly Language Data Processing

Session 2
Cache basics
Caches on ARM processors
Optimization consideration

Exception Handlers for ARM application processors
Exceptions overview
Interrupts sources and priorities
Abort Handlers
SVC Handlers
Undef Handlers
Reset Handlers

Hands-on Lab session
Exceptions Handling
Peripherals Driver Design

Session 3
Memory Management
Memory Management Introduction
Access Permissions and Types
Memory Protection Unit (MPU)
Memory Management Unit (MMU)
Optimizations & Issues

Using the NEON co-processor
NEON Instruction Set Overview
NEON Software Support

Writting C for ARM
Parameter Passing
Floating Point Linkage
Coding Considerations

Session 4
Synchronization Support
Synchronization primitives
SWP Instruction
LDREX / STREX and CLREX Instructions

Embedded software development
An out-of-the-box” build
Tailoring the C library to your target
Tailoring image memory map to your target
Reset and Initialization
Further memory map considerations
Building and debugging your image

Software Engineer’s Guide to Zynq
Zynq Peripherals
Cortex-A9 Pipeline
Media Processing Engine
Register Renaming
Fast Loop Mode
Program Flow Prediction
Preformance Monitoring Unit
Level One Memory System

Session 5
MPCore Logic
MPCore Features
Snoop Control Unit
Accelerator Coherency Port (ACP)
Interrupt Controller
Timer and watchdog
TrustZone Support
Developing for ARM MPCore Processors
Booting SMP
Configuring an interrupt

TrustZone Overview
Exception Handling
Memory System
Software Implementation

Lab Exercises:
The learning is reinforced with unique Lab Exercises using the Zynq QEMU virtual platform and covering assembly programming and bringing a complete bare metal system to life.

Lab exercises for assembly programming cover the concepts of data transfer, data processing, flow control and DSP instructions, and rely on the default development tool-set offered by Xilinx as well as a remote debug session based on a combination of GDB and the Zynq QEMU platform used for fast prototyping.

Additional exercises show the main steps involved in bringing a bare metal system to life, including the configuration of the various mode stacks and the creation of an interrupt handler. These exercises make use of the assembler and linker as well as the interactive debugger (GDB/CGDB and QEMU).

  • 0 Days
  • 0 Units
  • 0 Hrs

Select Your Currency

WOOCS 1.1.8
Drop Us A Query
[contact-form-7 id="5639" title="Drop Us A Query"]
Create an Account