TOPICS

Training materials
This class uses training materials developed by ARM®.
Content
Day 1
Introduction to ARM

Cortex-M0+ Overview

Tools Overview for ARM Microcontrollers
Toolchain • Models • Debug & Trace • Development Boards

v6-M Programmer’s Model
Data types • Core registers • Modes • Exceptions • Instruction • Set Overview

v6-M Memory Model
System Caches • Write Buffers • TCMs • Memory Types • Endianness • Address Map

Day 2
v6-M Exception Handling
Exception Model • Interrupts • Interrupt Handling • Prioritization and Control • Writing the Vector Table and Interrupt Handlers • Internal Interrupts and RTOS Support • Fault Exceptions

v6-M Compiler Hints and Tips
Basic Compilation • Compiler Optimizations • Coding Considerations • Mixing C/C++ and Assembler • Local and Global Data issues

CMSIS Overview
CMSIS-CORE • CMSIS-DSP • CMSIS-RTOS • CMSIS-SVD • CMSIS-DAP

SysTick Timer
Built-in Functions • Calibration Examples

Day 3
AMBA AHB-Lite
AHB Evolution • AHB-Lite Bus Protocol • AHB Signals

Processor Core
Processor Pipeline • Instruction Execution

System Interfaces
Memory System Bus Interfaces Details • Processor and Integration Levels

Integration Example
Wake-up Interrupt Controller • Debug Access Port • Micro Trace Buffer • Clock Gating

Power Management
Architectural Clock Gates • Sleep Modes • Power Domains • System Control

Cortex-M0+ Debug
Introduction to Debug • Debug Access Port (DAP) • Breakpoints/Watchpoints & Vector Catch • Cortex-M0+ Debug • System Control

Memory Protection
Memory Types • Memory attributes • Memory Protection Regions Configurations

Trace
MTB Operations • Register Description • Signal Description • Implementation Issues

Implementation and Integration
RTL Configuration • Design Flow Step • Reference Methodologies ARM and Cortex-M0+ are registered trade marks of ARM Holdings Plc..