Course materials
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Structure and Content
The Verification Landscape
How properties fit with verification • Simulation • Code coverage • Constrained random test generation • Functional coverage • Hardware verification languages • Assertion languages • Accellera standards • Formal verification • Property checking • Assertion-based verification

Properties Defined
Properties • Assertions • Simulation checkers • State space exploration • Assumptions and restrictions in static property checking • Verification coverage and corner cases • Assume-guarantee methodology • Assertion coverage • Automatic properties

Methodology and Benefits
Who writes properties? • Properties and the specification • Properties for the design and verification engineers • Observability and bug localisation • Property re-use • Debugging properties • Assertion density • Impact on documentation standards and review

The PSL Language
The boolean, temporal, verification and modelling layers • VHDL and Verilog flavours • Clocks • Verification directives • Verification units • Named properties • Safety and liveness properties • Simulation issues and the simple subset • The practicalities of using PSL with an HDL simulator

Temporal Operators
Learning common temporal operators by example • always • never • next • eventually! • rose(), fell() and prev() • until • before • abort • Operator precedence • Practising the use of these operators to write common properties

Sequences and Sequential Extended Regular Expressions • Sequence implication • Repetition operators • Parameterised sequences • Sequence composition operators • Practising the use of the typical form for a PSL property

Developing a Methodology
Functional coverage • Assessing coverage • Refining assertions • Transaction based assertions

Real Applications
Reusable assertions • Test modules • AMBA example

Further Features
The Foundation Language and Optional Branching Extensions • LTL and CTL operators • Further sequence operators • Ranges • Non-consecutive and goto repetition • Endpoints • next_event • whilenot • within • forall • Macros • The Verilog modelling layer • (These features are not necessarily supported by all current verification tools).

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