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Course materials
Course materials are renowned as the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world and has made them sought after resources in their own right. Course fees include:
Fully indexed course notes creating a complete reference manual
Workbook full of practical examples to help you apply your knowledge
Golden Reference Guide for Verilog language, syntax, semantics and tips
Tool tour guides (to support the tools and technologies used on the course).

Structure and Content
Introduction to Verilog
What is Verilog? • Scope of Verilog • Design flow for ASICs, CPLDs and FPGAs • Introduction to synthesis • Synchronous design • Timing constraints • Verilog books and internet resources

Modules
Modules & ports • Continuous assignments • Wire assignments • Comments • Names • Nets and strengths • Design hierarchy • Module instances • Primitive instances • Text fixtures • $monitor • Initial blocks • Variables

Nets and Values
Primitives • Wire assignments • Net types • Drive strengths • Logic values • Vectors • Numbers • Truncation • Signed numbers

Formatting, Timescale and Always
Output formatting • Timescales • Always blocks • $stop and $finish • Using wires and registers correctly

Always Blocks
RTL always blocks • Event control • Combinational logic sensitivity • If statements • Begin-end • Incomplete assignment and latches • FPGAs and latches • Unknown and don’t care • Conditional operator • Tristates

Procedural Statements
Case • casez • casex • full_case • parellel_case • For, repeat, while and forever loops • integers • Self-disabling blocks • Combinational logic synthesis

Clocks and Flipflops
Synthesising flip-flops & latches • Avoiding simulation race hazards • Nonblocking assignments • Asynchronous & synchronous resets • Clock enables • Synthesizable always templates • RTL synthesis technology • Inferring flip-flops • Making best use of RTL synthesis

Operators and Parameters
Bitwise, reduction, logical and equality operators • Part selects • Concatenation & replication • Shift registers • Conditional compilation • include • Parameters • localparam • Hierarchical names

FSM Synthesis
State transition diagrams • State machine architectures • FSM timing • Coding FSMs in Verilog • State encoding • One-hot state machines • Unreachable states & safe design practices

Arithmetic and Synthesis
Arithmetic operators and their synthesis • Vector arithmetic • Bit-length of expressions • Signed and unsigned values • Adder architectures • WYSIWYG arithmetic synthesis • Arithmetic optimization • Resource sharing

Tasks, Functions and Memories
Tasks • Task argument passing • Static vs automatic storage • Synthesis of tasks • Functions • Verilog memories • RAM modelling and synthesis • Inference vs instantiation • $readmemb and $readmemh • generate for/if/case •

File I/O
Writing to files • $display • $strobe • $write • $monitor • Opening a closing files • File descriptors • Reading from files • $fscanf • Raw file I/O • $fgets • $fgetc • $fseek • $ftell

Functional Simulation
Design flow through to P&R • Gate-level simulation • Back annotation using SDF.• PLD and ASIC design flow • Verilog libraries • Command-line options • Test benches • Comparing actual vs expected outputs • Behavioural modelling

Behavioural Verilog
Algorithmic coding • real • event control • wait • Named events • Fork & join • External disable • Intra-assignment timing controls • Overcoming clock skew • Continuous procedural assignment • defparam • Hierarchical names

Specialised Topics
Structural Verilog • Using built-in primitives • Gate, net & path delays • Specify blocks • State-dependent delays • Pulse rejection • Cell library modelling • library • liblist • config • The Verilog PLI • PLI applications • PLI routines • The PLI in practice • The VPI

SystemVerilog
Overview of SystemVerilog • Status of SystemVerilog • RTL enhancements • Interfaces • Assertions • Testbenches • C interface.

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