TOPICS

Training materials
Class materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world, and has made them sought after resources in their own right. The materials include:
Fully indexed class notes creating a complete reference manual
Workbook full of practical examples and solutions to help you apply your knowledge
SystemVerilog Golden Reference Guide for language, syntax, semantics and tips
LearnChase UVM Golden Reference Guide

Structure and Content

SystemVerilog Fundamentals (Day 1)
Introduction
What is SystemVerilog? • Language Evolution • SystemVerilog versus Verilog • Reg, Logic, and Bit • Variables, Wires, and Ports • SystemVerilog Language Features • Caveats • The UVM Family Tree •BOOKS and Resources

Programming Language Features
C-Like Language Features • Static vs Automatic Variables • Static vs Automatic Tasks • ++, –, and Assignment Operators • Labeling • Time Units • Do While Loop • Enhanced Tasks and Functions • Task and Function Arguments • Void Functions • Argument and Return Types • Type string • $sformatf

Basic Data Types
4-state and 2-state Types • Caveats with Signed Types • Initial Values • Every variable and wire has a well-defined initial value • Enumerations • Type-Checking of Enumerations • struct • typedef struct • Packed Struct • Packed and Unpacked Arrays • Indexing Multidimensional Arrays • Packages • Packages and Ports

Interfaces
Modelling a Bus • APB with Master and Single Slave • Modelling APB using Ports • Simple Interface = Bundle of wires/vars • Using an Interface • Accessing Interface Members • Modports • Modport Directions • Connecting Interfaces with Modports • Generic Interface Ports • Ports and Parameters to Interfaces

Clocking Blocks
Input and Output Skew • Creating a Clocking Block • Testbench and Clocking Block • Cycle Delays and Clocking • Input and Output Skew Syntax Summary • Scheduler Regions • Stimulus and Response • Signal Aliasing • Multiple Clocking Blocks • Driving a Net • Clocking Blocks in Interfaces • Clocking Blocks versus Programs

Arrays and Queues
Dynamic Arrays • Queues • Working with Queues • Queue Methods • Associative Arrays • Associative Array Methods • Foreach

Class-Based SystemVerilog (Days 2-3)
Classes for Transactions
Constrained Random Verification • Representing Transaction Data • SystemVerilog Classes • Object = Instance of Class • Initializing Objects • Constructor Arguments • Static Data Members • Constant Data Members • Randomized Data Members • Data Members of Class Type • Forward Typedef • Object Copy with new • Shallow Copy • Deep or Shallow Copy?

Virtual Interfaces
Test Harness and Testbench • Modules versus Classes • Creating the Testbench • Virtual Interface • Building a test harness • Adding a clocking block • Virtual interface • Connecting the virtual interface • Accessing a Task through a Modport • Testbench Static Structure • BFM or Driver Class • Testbench Object Structure

Extending Classes for Stimulus
Improved Generator Class • Constrained randomization • Creating an Extended Class • The Inheritance Relationship • Inheriting Class Members • Jargon • Control Knobs and Constraints • Methods of Extended Class • Derived-class Object, Base-class Variable • Virtual Methods • General-Purpose Infrastructure

TLM and Channels
Reusable Verification Environments • Transaction Level Modelling • Using Channels • Generic Channel and Transaction Classes • Out-of-Block Declarations • Connecting Channel • Getting Data from a Generic Channel • Safe Downcasting with $cast • Type Parameterization of Classes • Running Components with fork…join • fork…join_none • Identifying Forked Processes

Component Hierarchy
Testbench Component Hierarchy • Implementing Relationships • Base Classes (review) • Abstract Class and Pure Virtual Methods • Component Base Class • Launching a Task with fork…join_none • Customising a Component • Constructing a Component

Functional Coverage
Coverage Driven Verification • Verification Planning • From Features to Tests • Covergroups • Embedded Covergroups • Procedural Sampling • Arguments and Options • Coverage Bins • Cross Coverage • Cross Coverage and Labels • Cross Coverage Example • Controlling Cross Bins • Transition Coverage

More on Constraints
Inline Constraints • Overriding Constraints • Procedural Control of Randomization • Procedural Control of Constraints • Constraint Ordering • Function Calls within a Constraint • Constraining Dynamic Arrays • Constraining an Array-of-Objects • Arrays within a Constraint • Hierarchical Constraints

SystemVerilog Assertions
Property versus Assertion • Immediate and Concurrent Assertions • Action Blocks and Severity • Concurrent Assertions • Temporal Behaviour • Clocks and Default Clocks • |=> and |-> • $past • Sequences • Concatenation and Repetition • Simulation of Assertions

Applying UVM (Days 4-5)
Introduction to UVM
The Universal Verification Methodology • The UVM Open Source Standard • UVM Highlights • Tests versus Testbench • Configurable Verification Components • UVM Class Hierarchy • UVM Basic Simulation Phase Methods • Alternative Run Phases • Phase Synchronization • Customization – The Factory • TLM Connections • Required / Provided Interfaces • Push vs Pull Connections • Layered Sequential Stimulus • Virtual Sequences • Learning and Using UVM

Getting Started with UVM
Simple Testbench Architecture • Sequence Item Class • Methods of a Transaction Class • Overriding do_compare • Alternative – Field Macros • Sequence Class • Alternatives: Do Macros or Function Calls • Objections • Driver • Driver run_phase Task • Simple Testbench Architecture • Environment – Constructor • Environment – Build Phase • Environment – Connect Phase • Configuration Database • DUT Interface • The Config Database • Connecting the Virtual Interface • Test Class – build_phase • Test Class – run_phase • Top-Level Module • Running a Test

Writing Tests
Easier UVM Coding Idioms • Starting a Sequence from a Test • Wildcard Searches • Nested Sequences • Child Sequence • Child Sequence Body • Parent Sequence • p_sequencer • Sequence Macros • From the Driver’s Side • Sequence-Driver Interaction • Configuration • Creating a Configuration Object • Getting the Configuration Object • Extending an Existing Class • Factory Overrides • Selecting the Test from the Command Line

Monitors, Reporting, and TLM
Driver versus Monitor • Monitor Class • Monitor Run Task • Reporting • Report Macros • Controlling Verbosity • Setting Actions • Severity and Actions • Scope of Actions • Writing to a Log File • The Reporting Set Methods • TLM Ports, Exports, and Imps • Port-Child Port Binding • Export-Child Export Binding • Implementing an Export • Monitor with Devolved Tasks • Analysis Ports • Monitor with Analysis Port • Subscriber • Registering Subscribers

Checkers and Scoreboards
Example Design • Separating Test from Test Harness • Interfaces • Modports • Bus Cycles • Bus Properties • Adding ISS Reference Model • Sampling Bus in Interface • Bus Monitor Class • Detecting Bus Sequence • Bus Monitor run Task • ISS • Verification Environment • Scoreboard • Comparator Input Requirements • Field Macros • Field Macro Flags • Overriding do_compare • Field Macros and Overridden Methods • Overriding do_pack • Redirecting Reports

Functional Coverage & End-of-Test
Coverage Collection • Detecting States in Bus Monitor • Embedded Covergroups in UVM • Plumbing the Coverage Collector Class • Analysis Subscriber Classes • TLM imp Macros • Coverage on Internal States of DUT • Objection Mechanism • Raising and Dropping Objections • Objections in Sequences • Objection Drain Time

Configuring the Testbench
Constrained Random Generation • Factory Overrides “By Name” • Regular Expressions and Globs • Parameterized Components • The Configuration Database • Verilog / VHDL versus UVM • Setting Configuration Table Entries • Getting Configuration Table Entries • Multiple Configuration Tables • Debugging Configuration Settings • Configuration Objects • UVM Command Line Processor • Standard Command Line Arguments

Agents and Virtual Sequences
Agent Architecture • UVM Agent • Agent Build • Connecting Agent Components • Configuring an Agent • Starting a Sequence Automatically • Virtual Sequences and Sequencers • Virtual Sequence • Starting Virtual Sequence from Test

More on Sequences
Sequence Callbacks • Virtual Sequences Revisited • Locking a Sequencer • Calling Lock/Grab • Request and Response • Pipelined Responses in the Sequence • Pipelined Responses in the Driver • Reponses with Layered Sequencers • Layering Sequences and Agents • The Layering Sequence • Multiple Agents / Sequencer Stacks • Transaction Recording • Reports within Sequences

Appendix (extra topics for reference)
The Report Catcher • Registering Report Catchers • Blocking put, get, and peek • Blocking versus Non-Blocking Methods • uvm_tlm_analysis_fifo • Subscriber with uvm_tlm_analysis_fifo • Subscriber with FIFO Implementation • Stopping a Test – OVM Legacy • Barriers and Barrier Pools • Setting the Threshold • UVM Tests and DUT REGISTERS  • UVM Register Layer • Register Block & Address Map • A Register Sequence • User-Defined Register Test • UVM Simulation Output.