TOPICS

Course materials
LearnChase course materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the HDL training world, and has made them sought after resources in their own right. The materials include:
Fully indexed course notes creating a complete reference manual
Lab files comprising the complete SystemVerilog source files and scripts

Structure and Content
Introduction
The evolution of VMM from the VMM book through VMM 1.1 to VMM 1.2 • overview of the VMM testbench architecture • main features of VMM 1.2

Transaction Communication
Defining transactions using vmm_data • shorthand macros • vmm_channel • the active slot • transaction completion models • TLM 2.0 communication • TLM ports and exports • analysis ports • sockets • the generic payload • VMM recommended guidelines

The VMM Environment
Virtual interfaces • clocking blocks • Using vmm_env • Using vmm_group • explicit phasing • implicit phasing • vmm_xactor • starting and stopping transactors • master and slave transactors • the atomic generator • running a test • programs

Configurability
Hierarchical name matching • searching object instances • class factory • factory overrides • callbacks • extending a callback façade • registering callbacks • order of callback execution • configuration database • vmm_opts • configuration macros • setting a virtual interface • command line options

Messaging
vmm_log • using the message service • built-in message macros • types and serverities • message handling • message catching • redirecting to a file • notifications • vmm_notify • indicate and wait_for • synchronization mode • notify callbacks • built-in notifications • using vmm_consensus • explicit vs. implicit consensus mechanism

The Datastream Scoreboard
Using the datastream scoreboard • overriding transform and compare • comparison modes • creating monitors • using TLM analysis exports • defining export implementations • handling multiple streams • using iterators

The Scenario Generator
Understanding scenarios • vmm_scenario_gen • using the apply method • the scenario set • scenario identifiers • executing a scenario • using scenarios in tests • configuring scenario generators • using the configuration database with scenarios • creating hierarchical scenarios • single stream scenarios • multi-stream scenarios • registering channels with a generator • exclusive channel access

The Register Abstraction Layer
The RAL register model • RALF and ralgen • RAL-based environments • predefined register tests • register coverage

vmm_subenv and vmm_consensus
Reusing verification environments • using vmm_subenv • using vmm_group • scalable end-of-test mechanism • using explicit phasing • using implicit phasing • the memory allocation manager.